How to Create Area Constraints for Kernel in Vitis Accelerated Design

This article is from Hong Han, senior product application engineer of Xilinx

The platform on alveo series development board is actually a static part of DFX design. Alveo series development board is used in Vitis unified software platform to design accelerated kernels. Finally, the logic of these kernels will be distributed in the dynamic area of DFX design.

This article will introduce how to make a floorplan (draw pblock) for the kernel logic and artificially control the layout of the kernel logic.

Let's take the classic example design "vector addition" as an example:

1. Open Vitis 2020.2 and create a new application project

File -》 New -》 Application project

2. Select Xilinx_ u200_ qdma_ 201910_ 1 Platform (the method discussed in this article is not limited to a specific platform)

3. Select and open example design "vector addition"

4. Set "- R2" for hardware flow in link phase, and then build

Select - R2 for report level here: the VPL (Vitis platform link) process outputs more intermediate files. Later, we will use opt.dcp required to draw kernel pblock

5. The VPL completes opt without waiting for the xclbin file to be generated_ After the design step, we can see XX_ Opt.dcp file.

XX_ Directory and file name of opt. DCP:

vitis_ pblock_ u200/vadd_ test_ system_ hw_ link/Hardware/binary_ container_ 1.build/link/vivado/vpl/prj/prj.runs/impl_ one

pfm_ top_ wrapper_ opt.dcp

6. Put this XX_ Copy opt.dcp to another directory and open the DCP file with vivado

7. View the existing pblock. Main menu window - physical constraints

In this view, you can see that the platform has set corresponding pblocks in each SLR for the dynamic area, and it should be noted that the existing pblocks in the design are hierarchical

For example: pblock_ dynamic_ Region contains three subordinate pblocks:

pblock_ dynamic_ SLR0,

pblock_ dynamic_ SLR1,

pblock_ dynamic_ SLR2,

Reminder: the number of SLRs may be different on different platforms. It is normal that the names of pblock in different platforms are different. Users need to observe.

The pblock generated for the kernel module should be pblock_ dynamic_ Slr0 is a sub module of pblock. The tool supports placing different parts of the same kernel into multiple SLRs. Users need to ensure the timing of cross SLR paths.

8. Draw pblock for the kernel module

Here, try to put the kernel in pblock_ dynamic_ The central area to which slr0 belongs

《1》。 Select the kernel module in the netlist view of vivado

The module name in the example is PFM_ top_ i/dynamic_ region/krnl_ vadd_ one

《2》。 You can see in the cells properties window that the current pblock of this module is pblock_ dynamic_ region

《3》。 Click the "draw pblock" button in the device view to the original pblock in the device view_ dynamic_ Draw a box within the range of slr0, and the area covered by the newly drawn pblock shall be completely included by the original pblock. After drawing, you can also select pblock to fine tune the boundary of pblock. At the same time, in order not to affect the structure of the original pblock, set the parent pblock of the new pblock to pblock with the following command in TCL console_ dynamic_ SLR0:

set_ property PARENT pblock_ dynamic_ SLR0 ï¼»get_ pblocks pblock_ krnl_ vadd_ 1ï¼½

《4》。 Look at the pblock attribute of the kernel module. It has changed to pblock_ krnl_ vadd_ one

《5》 The corresponding constraints of pblock will be printed in TCL console. We can copy these constraints to a new TCL file and save them.

(save it here to kernel_pblock. TCL)

《6》 Take a look at the updated pblock structure and the newly generated pblock_ krnl_ vadd_ 1 is pblock_ dynamic_ Child pblock of slr0

《7》 Continue to execute place on TCL console_ The design command completes the layout

Theoretically, this step can be skipped if you are sure that there is no problem with your pblock.

《8》 Complete place_ After designing, you can observe the actual distribution of kernel resources on the device

You can see that all the kernel logic is distributed in the pblock area just drawn

9. In the link phase of Vitis, make the following settings to make the previously saved command to draw pblock in the place of VPL (Vitis platform link)_ The design step takes effect before execution

--vivado.prop run.impl_ 1.STEPS.PLACE_ DESIGN.TCL.PRE=XX/kernel_ pblock.tcl

10. Rebuild the hardware flow of Vitis, and the previously added commands will take effect.

Summary: This is a simple process of creating area constraints (pblocks) for kernel logic. Actual users can also create pblocks for sub modules of the kernel. There are no restrictions on tools in this regard

Editing: JQ

How to Create Area Constraints for Kernel in Vitis Accelerated Design 1

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